1. Technical Field
The present invention relates to data transfer control apparatuses, such as DMA controllers, for controlling transfer of data to or from a DRAM.
2. Description of the Related Art
When a DRAM (Dynamic Random Access Memory) and a peripheral device exchange data directly with each other, a DMA (Direct Memory Access) technology is often utilized. The DMA technology allows data transfer independently of a CPU (central processing unit). When DMA is activated after a transfer start address and a transfer number are designated, an entire transfer is divided into units referred to as “commands” that designate an address, a data transfer direction, and a burst number which are optimized for the DRAM, and repeats the issuance of the commands and data transfer until the designated transfer number is reached. It is known that a certain delay (latency) is caused between command issuance and completion of data transfer. In recent years, a DMA controller (DMAC) has been proposed whereby, in order to prevent the decrease in bus utilization efficiency due to the delay, the phase of command and that of data are separated so that the command can be issued beforehand.
For example, Japanese Laid-Open Patent Publication No. 2009-217640 (which may be hereafter referred to as “Patent Document 1”) discusses a data transfer control apparatus (DMAC) having a cache memory and capable of prior issuing of command. In this DMAC, it is determined whether data corresponding to an inputted address exists in the cache memory, so that the number of times of access to the DRAM can be reduced and data transfer efficiency can be improved. In this DMAC with the prior command issuing function, however, there still remains the problem of a long delay time between the issuance of a first command after activation of DMA and the acquisition of data by accessing the DRAM. As a result, bus utilization efficiency cannot be sufficiently increased when DMA is activated a number of times.
Thus, while Patent Document 1 attempts to improve data transfer efficiency by reducing the number of times of access to the DRAM in the DMAC having a cache memory, the problem of a long delay time between the issuance of the first command after activation of DMA and the acquisition of data by accessing the DRAM remains unresolved.